
`timescale 1ns/1ns

module blink_led #( parameter BLINK_PERIOD = 31_250_000 - 1)
(
    input         clk,
    input         rst,
    input         xfer_state,
    output reg    led_en
);
localparam       TCQ = 1;  // Clock-to-out delay
reg   [24:0]  cnt_clk;
reg   [7:0]   cnt;
reg   [7:0]   cnt_last;

always @(posedge clk ) begin
    if ( rst ) begin
        cnt_clk     <= #TCQ 25'b0;
    end else begin
        if ( cnt_clk == BLINK_PERIOD  ) begin
            cnt_clk <= #TCQ 25'b0;
        end else begin
            cnt_clk <= #TCQ cnt_clk + 1'b1;
        end
    end
end

always @(posedge clk ) begin
    if ( rst ) begin
        cnt         <=  #TCQ 8'd0;
        cnt_last    <= #TCQ 8'd0;
        led_en      <= #TCQ 1'b0;
    end else begin
        if ( cnt_clk == BLINK_PERIOD  ) begin
            if ( cnt_last != cnt ) begin
                cnt_last    <= #TCQ cnt;
                led_en      <= #TCQ !led_en;
            end else begin
                led_en      <= #TCQ 1'b0;
            end
        end else begin
            if ( xfer_state ) begin
                cnt <= #TCQ cnt + 1'b1;
            end
        end
    end
end

endmodule




  

